Room and Low Temperature Performance of High-speed Neural Network Circuits
نویسندگان
چکیده
We have described a challenging neural-network hardware implementation that would mate a 64x64-pixel infhred sensor directly on to a 3-dimensionally packaged set of neural processing chips with parallel input for high speed image processing. We now describe two enhanced schemes. In one the synapse (analog multiply device) resolution has been increased from 7to 8-bit without increasing the silicon area but requiring low temperature (77K) operation. In other an innovative chip is incorporated in place of the mated infrared sensor array that permits detachtnent of the IR sensor without compromising the input speed. This permits room temperature operation of the processor for a projected image processing speed of a tera-operations per second (TOPS). We compare the 7and 8-bit synapse architectures and provide the test results of the operation (linearity and speed) both at low and room temperatures. Non linearity effects and range compression issues are also discussed.
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